In recent years, unconventional nonvolatile memory (NVM) devices, such as ferroelectric random access memory (FRAM) devices, phase-change random access memory (PRAM) devices, and resistive random access memory (RRAM) devices, have emerged. In particular, RRAM devices, which exhibit a switching behavior between a high resistance state and a low resistance state, have various advantages over conventional NVM devices. Such advantages include, for example, compatible fabrication steps with current complementary-metal-oxide-semiconductor (CMOS) technologies, low-cost fabrication, a compact structure, flexible scalability, fast switching, high integration density, etc.
As integrated circuit (IC), including such RRAM devices, has been desired to be more powerful, a number of the RRAM devices in the IC is desired to be maximized accordingly. Generally, an RRAM device includes a top electrode (e.g., an anode) and a bottom electrode (e.g., a cathode) with a variable resistive material layer interposed therebetween. Forming the RRAM device in such a stack configuration may encounter a limit in terms of maximizing the number of the RRAM devices in the IC since the number can only be increased two-dimensionally. Alternatively stated, within a given area on the IC, the number of the RRAM devices may be substantially limited. Thus, existing RRAM devices and methods to make the same are not entirely satisfactory.